Reconfig in VMM

During one ofour recent VMM trainings at a customer site at Pune, a nice question popped up. How to handle reconfig in a standard VMM env? While conceptually it is simple, customer wanted a ready made example. We will be creating an example pretty soon to demo this.

Ajeetha, CVC
www.noveldv.com

Fast-Track course on Verification Using SystemVerilog - Bangalore

Fast-Track course on Verification Using SystemVerilog - Bangalore

Quick facts

When: 6^th or 7^th June (Fri/Sat)

Where: Bangalore, CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)
Cost: Rs. 2500 /- onwards (See below for details)

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-41495572

What’s SystemVerilog?

IEEE 1800, SystemVerilog is the de-facto language for Digital system Verification (and Design). Almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.

What’s a Fast-Track course?

A Fast-Track process is intended to cut short detailed explanations aimed at getting to the core of the subject ASAP. CVC’s Fast-Track courses are intended for engineers with little extra time to spare, yet would like to learn the new and advanced verification techniques. In 1-day we cover the essential sub-set of SystemVerilog and enable to you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification. As it is really time bound we will not delve into rationales on many aspects, instead will focus on getting you hands-on with the language.

Who should attend?

Practicing Design and Verification engineers with tight project schedules are ideal attendees. DV managers will equally find it useful as they can grasp the complexity of SV in 1-day without bothering about the nitty-gritty in great detail.

What’s the cost?

That is a no-brainer question, isn’t it? We understand and appreciate the cost conscious landscape of our region. That’s why we have innovative cost structure as shown below.

The basic cost of this course is Rs. 4,000 /- per attendee. As a limited period offer, we are glad to announce “The more-the-merrier” scheme. If you pool in more folks you get more discounts. For every other attendee that you bring along, you get Rs. 500 /- discount – for BOTH the attendees (subjected to a minimum of Rs. 2500 /-), can it get better than this :-) ?

Here is a simple table showing the offer in numeric:

No. of attendees | Cost per attendee | Your savings (total)

2 3500 1000

3 3000 3000

4 (and above) 2500 6000+

Venue details

CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)
Date: 2 potential dates:

Friday 6^th June at 8.30 AM

Saturday 7^th June at 8.30 AM

How do I register for a class?

To attend this class, confirm your registration by sending an email to cvc.training @ gmail.com. +91-9916176014, +91-80-41495572

Please include the following details in your email:

Name:
Company Name:
Official Email ID:
Contact Number:

Preferred Date: 6^th or 7^th June (Friday or Saturday)

Are there extended versions of these courses?

Of-course yes! Our flagship trainings on Verification Using SystemVerilog are originally designed for 3 variants:

• · A 10-day class with extensive labs and a complete project (suitable for students, jobseekers)
• · A 3-day class and
• · A 2-day class

So, depending on how much time you can invest, you pick the one appropriate to you. Needless to say – the more time you invest, the better you master this amazingly powerful language.

Trainer Profile
Ajeetha Kumari, Design Verification Consultant
* Has 8+ years of experience in Verification
* Co-authored leading books in the Verification domain.
* Presented papers, tutorials in various conferences, publications and
avenues.
* Worked with all leading edge simulators and formal verification
(Model Checking) tools.
* Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDV
and OOP for Verification
* Holds M.S.E.E. from prestigious IIT, Madras.

VMM is now Open Sourced!!

For all the verification enthusiastic folks, this is a great news, see: www.vmmcentral.org. CVC is organizing series of lectures and trainings around VMM, stay tuned to this blog or www.noveldv.com for more!

Ajeetha, CVC
www.noveldv.com

A Pragmatic Approach to VMM Adoption
.......A SystemVerilog Framework for Testbenches

This book is intended for engineers involved in the increasingly important task of verifying the functionality of complex digital electronic circuits. It provides background on the coverage- driven, constrained-random verification environments detailed in the VMM book and offers advice on adoption and deployment. The book presents by example the practical application of the VMM methodology using SystemVerilog.

"Our experience with the VMM methodology has been very positive because it requires a minimal knowledge of object-oriented programming to put the verification effort where it belongs -- into the problem at hand," said Ben Cohen, co-author of "A Pragmatic Approach to VMM Adoption, VhdlCohen Publishing." "It also brings a common look and feel to every VMM-based verification environment and provides a mature framework that has endured years of active use."

"A Pragmatic Approach to Adopting VMM" is intended to help design and verification engineers come up to speed in the design of SystemVerilog transaction-based testbenches that comply with the VMM for SystemVerilog. With complete, compilable and executable examples, it will help users adopt the VMM methodology in the creation of comprehensive constrained-random and directed verification environments using a transaction-level modeling approach. All code examples are available for download. The book makes use of the most practical rules of the VMM methodology to demonstrate and show how to create a VMM-compliant testbench.

"One of the reasons that we decided to write 'A Pragmatic Approach to Adopting VMM' is because we truly believe that the VMM methodology is a framework that allows you to quickly create fast, reusable, and extendable testbenches using SystemVerilog," continued Cohen. "This book adds some additional explanations and practical, complete examples to emphasize the features of the VMM methodology. This book also presents the results of real- life experiences applying the methodology to various problems, providing useful insight and enabling faster SystemVerilog testbench adoption."

The book demonstrates features and techniques that support transactions, generators, command transactors (such as bus functional models), logging of messages, and the verification environment. Since SystemVerilog includes object-oriented programming (OOP) capabilities, the book provides applications of OOP design patterns such as factories and callbacks. In addition, it addresses advanced topics that relate to different applications and verification, including the synchronization of events through the notification services, channel broadcast, channel scheduling, and the role of coverage.

"The advanced techniques detailed in the VMM for SystemVerilog deliver tremendous value in terms of verification productivity and predictability, but some training is helpful at making adoption as quick and easy as possible," said Janick Bergeron, Synopsys Scientist. "I am pleased to welcome 'A Pragmatic Approach to Adopting VMM' to the canon of VMM-related literature. I hope users will find it helpful in appreciating the power of the VMM methodology and ease their adoption of it."

"'A Pragmatic Approach to Adopting VMM' can be seen as a practical review of best practices for writing SystemVerilog-based testbenches," said Alain Raynaud, Technical Director, EVE USA, Inc. "Companies should adopt the VMM methodology, if only to save cost, as verification engineers have better things to do than redevelop and learn a new testbench environment every time they change projects."

"A Pragmatic Approach to VMM Adoption: A SystemVerilog Framework for Testbenches" is available now from VhdlCohen Publishing for $125 US. To find out more about the book or to order it online, please visit: http://www.systemverilog.us/vmm_info.html .

All trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

For India purchase contact: Ajeetha Kumari ajeetha @ gmail.com +91-80-41495572

Web site: http://www.noveldv.com